Verilog Implementation of XOR Gate

Introduction:-

Verilog Implementation of XOR Gate

The XOR door (some of the time EOR entryway, or EXOR entryway and articulated as Exclusive OR entryway) is a computerized rationale entryway that gives a genuine (1 or HIGH) yield when the quantity of genuine sources of info is odd. A XOR entryway actualizes an elite or; that is, a genuine yield comes about in the event that one, and just a single, of the contributions to the door is valid.

Verilog Code For XOR Gate:-

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: VHDL Language
// Engineer: Manohar Mohanta
// 
// Create Date:    19:06:55 11/16/2017 
// Design Name:  XOR Gate
// Module Name:    xor_gate 
// Project Name:  1-bit XOR Gate
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module xor_gate(
    input a,
    input b,
    output c
    );

assign c=a^b;

endmodule

Simulation Result For XOR Gate:-