Verilog Implementation of 2-bit Vedic Multiplier

Vedic Multiplier 2-bit

The Vedic multiplier is designed by using the 2-bit gate level Vedic multiplier.The 2-bit gate level Vedic multiplier proposed in this project. By combining the four 2-bit Vedic multipliers, we have designed 4-bit Vedic multiplier. Normal 4-bit parallel adders are used to add the partial products of 4 2-bit Vedic multipliers.

You can Find the Code Where You can Learn How to implement it.

Code For Vedic Multiplier 2-bit

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:04:33 11/17/2017 
// Design Name: 
// Module Name:    vedic 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module vedic(
    input [1:0] a,
    input [1:0] b,
    output [3:0] q
    );
wire [3:0]s;

assign q[0]= a[0] & b[0];
assign s[0] = a[1] & b[0];
assign s[1]= a[0] & b[1];
assign q[1] = s[0]^s[1];
assign s[2] = s[0]&s[1];
assign s[3]= a[1]&b[1];
assign q[2]= s[2]^s[3];
assign q[3]= s[2]&s[3];

endmodule

Simulation Results:-

Vedic Multiplier Simulation Result

Demo For 2-bit Vedic Multiplier