Verilog Implementation of Multiple-Input Signature Registers: An Improved Design 8-bit

Introduction:-

            In worked in individual test (BIST) strategies, putting away all the circuit yields on chip isn't conceivable, however the circuit yield can be compacted to frame a mark that will later be contrasted with the brilliant mark (of the great circuit) to recognize issues. Since this pressure is lossy, there is dependably a plausibility that a defective yield likewise creates an indistinguishable mark from the brilliant mark and the issues can't be identified. This condition is called mistake concealing or associating. BIST is expert with a numerous information signature enroll (MISR or MSR), which is a kind of LFSR. A standard LFSR has a solitary XOR or XNOR door, where the contribution of the entryway is associated with a few "taps" and the yield is associated with the contribution of the principal flip-slump. A MISR has a similar structure, yet the contribution to each flip-slump is nourished through a XOR/XNOR door. For instance, a 4-bit MISR has a 4-bit parallel yield and a 4-bit parallel information. The contribution of the principal flip-tumble is XOR/XNORd with parallel information bit zero and the "taps". Each and every other flip-slump input is XOR/XNORd with the first flip-tumble yield and the relating parallel information bit. Thus, the following condition of the MISR relies upon the last a few states contradicted to only the present state. Subsequently, a MISR will dependably produce the same brilliant mark given that the info succession is the same unfailingly.

Abstract:-

           For testable design purposes, a multiple-output digital system needs a multiple-input signature register. This register accelerates the testing task by compressing multiple-input data streams into one signature. Existing designs depend on parallel feeding the input polynomials to the storage elements. These designs, give a good compression but, suffer from some drawbacks. The presented paper proposes a new design for the multiple-input signature register. This proposed design aggregates all inputs at a certain point and feeds them to the shift register. By adopting this concept, we are able to improve the operation of the multiple input signature register in a number of ways. Complete VHDL modeling and simulation for the existing and the proposed designs verified the advantages of the new structure. 

Multiple-Input Signature Register

Code For Multiple-Input Signature Registers :-

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: VHDL Language
// Engineer: Manohar Mohanta
// 
// Create Date:    19:54:57 11/16/2017 
// Design Name:  Multiple-Input Signature Registers
// Module Name:    sig_reg 
// Project Name: Multiple-Input Signature Registers
// Target Devices: 
// Tool versions: 
// Description: Multiple-Input Signature Registers
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module sig_reg(
    input  [8:0]a,
  input clk,
  input rst,
    output  [8:0]y
    );
  //wire [7:0]w;
  //reg y;
  //wire f;
  wire [8:0]s;
//xor_gate xor14 (a[0],a[1],w[0]);
//xor_gate xor15 (w[0],a[2],w[1]);
//xor_gate xor16 (w[1],a[3],w[2]);
//xor_gate xor17 (w[2],a[4],w[3]);
//xor_gate xor18 (w[3],a[5],w[4]);
//xor_gate xor19 (w[4],a[6],w[5]);
//xor_gate xor20 (w[5],a[7],w[6]);
//xor_gate xor21 (w[6],a[8],w[7]);

xor_gate xor22 (a[7],y[8],s[0]);
d_ff dff1 (.d (s[0]),.clk (clk),.rst (rst),.q (y[0]));

xor_gate xor23 (a[0],y[0],s[1]);
d_ff dff2 (s[1],clk,rst,y[1]);

xor_gate xor24 (a[1],y[1],s[2]);
d_ff dff3 (s[2],clk,rst,y[2]);

xor_gate xor25 (a[2],y[2],s[3]);
d_ff dff4 (s[3],clk,rst,y[3]);

xor_gate xor26 (a[3],y[3],s[4]);
d_ff dff5 (s[4],clk,rst,y[4]);

xor_gate xor27 (a[4],y[4],s[5]);
d_ff dff6 (s[5],clk,rst,y[5]);

xor_gate xor28 (a[5],y[5],s[6]);
d_ff dff7 (s[6],clk,rst,y[6]);

xor_gate xor29 (a[6],y[6],s[7]);
d_ff dff8 (s[7],clk,rst,y[7]);

xor_gate xor30 (a[8],y[7],s[8]);
d_ff dff9 (s[8],clk,rst,y[8]);

endmodule

Simulation Results :-



Download Base Paper:-