Verilog Implementation of Transmission NOT Gate

CMOS Transmission Gate Example

A transmission door, or simply switch, is characterized as an electronic component that will specifically square or pass a flag level from the contribution to the yield. This strong state switch is contained a pMOS transistor and nMOS transistor.

Code For Transmission NOT Gate:-

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: VHDL Language
// Engineer: Manohar Mohanta
// 
// Create Date:    09:47:09 12/07/2017 
// Design Name: transmission_NOT Gate
// Module Name:    transmission_NOT Gate
// Project Name:  Basics of Verilog For B.Tech Students
// Target Devices: Any FPGA
// Tool versions: Xilinx 14.5
// Description: In this websie/App you will get to know more about basics of verilog or VHDL programs.
//
// Dependencies: No Dependencies
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments: Insperation by Gosala Anitha My True Love
//
//////////////////////////////////////////////////////////////////////////////////
module transmission_not(
    input a,
  input ctr,
    output b
    );
reg b;;
always @ (ctr,a)
begin
 if(ctr==1)
  begin
   b=~a;
  end
 else
  b=1'bz;
end
endmodule

Simulation Results of Transmission NOT Gate:-

Simulation results of Transmission gate