VHDL Implementation of Inverter or Not Gate

inverter (logic gate)

The inverter is a fundamental building obstruct in computerized gadgets. Multiplexers, decoders, state machines, and other advanced computerized gadgets may utilize inverters.

Code For Inverter

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-- Company: VHDL Language
-- Engineer: Manohar Mohanta
-- 
-- Create Date:    10:06:50 12/07/2017 
-- Design Name: Inverter
-- Module Name:    inv - Behavioral 
-- Project Name: Basics of VHDL For B.Tech Students
-- Target Devices: Any FPGA
-- Tool versions: Xilinx 14.5
-- Description: In this websie/App you will get to know more about basics of verilog or VHDL programs.
--
-- Dependencies: No Dependencies
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments: Insperation by Gosala Anitha My True Love
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inv is
    Port ( a : in  STD_LOGIC;
           b : inout  STD_LOGIC);
end inv;

architecture Behavioral of inv is

begin
b<=not(a);

end Behavioral;

Simulation Results:-

Output of Inverter