![inverter logic gate Verilog inverter logic gate](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhl9n4H4Tr2uGHZWm8xoRASHeBUfDVe2SmUh1y8_wE-3yXlOafEdXnhV5Bx0NH2oF-iORc3_a0Xpa1CIhlXCWo6AbrdrHFifatcAKqMVtDEV5kuHd7orooXD6daFAsaVdKLOcscMWdvH1LC/s200/120px-NOT_ANSI_Labelled.png) |
inverter (logic gate) |
The inverter is a fundamental building obstruct in computerized gadgets. Multiplexers, decoders, state machines, and other advanced computerized gadgets may utilize inverters.
Code For Inverter
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: VHDL Language
// Engineer: Manohar Mohanta
//
// Create Date: 09:47:09 12/07/2017
// Design Name: Inverter
// Module Name: inv
// Project Name: Basics of Verilog For B.Tech Students
// Target Devices: Any FPGA
// Tool versions: Xilinx 14.5
// Description: In this websie/App you will get to know more about basics of verilog or VHDL programs.
//
// Dependencies: No Dependencies
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments: Insperation by Gosala Anitha My True Love
//
//////////////////////////////////////////////////////////////////////////////////
module inv(
input a,
output b
);
assign b=~a;
endmodule
Simulation Results:-
![Simulation Results of Inverter Simulation Results of Inverter](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiJnhVNHs_f7Hubnt1a79PXO4gJfWxy3-6uNQ4FHdgxYMfx3w-aAw9FmlyB2PZ7A_GO-bcbfclD39H0vtAJ2W9h_xDn2ACqzG1fU-i16z9PjKX0cfzlWkE4eyCzYTkeIHpRhsC9jicTGSNO/s640/inverter.JPG) |
Output of Inverter |
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