Verilog Implementation of Buffer

Buffer

The buffer is a fundamental building obstruct in computerized gadgets. Multiplexers, decoders, state machines, and other advanced computerized gadgets may utilize buffer to store the values temporaryly.

Code For Buffer

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: VHDL Language
// Engineer: Manohar Mohanta
// 
// Create Date:    09:47:09 12/07/2017 
// Design Name: Inverter
// Module Name:    inv 
// Project Name:  Basics of Verilog For B.Tech Students
// Target Devices: Any FPGA
// Tool versions: Xilinx 14.5
// Description: In this websie/App you will get to know more about basics of verilog or VHDL programs.
//
// Dependencies: No Dependencies
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments: Insperation by Gosala Anitha My True Love
//
//////////////////////////////////////////////////////////////////////////////////
module inv(
    input a,
    output b
    );

assign b=a;

endmodule

Simulation Results:-

Output of Buffer