VHDL Implementation of J-K Flip-Flop

J-K Flip-Flop. The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge.

VHDL Code

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-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    09:04:55 06/04/2017 

-- Design Name: 

-- Module Name:    jk_ff - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity jk_ff is

    Port ( j,k : in  STD_LOGIC;

           clk : in  STD_LOGIC;

 reset : in STD_LOGIC;

            Q : out  STD_LOGIC;

           Qbar : out  STD_LOGIC);

end jk_ff;

architecture Behavioral of jk_ff is

signal qtemp,qbartemp : std_logic :='0';

begin

Q <= qtemp;

Qbar <= qbartemp;

process(clk,reset)

begin

if(reset = '1') then           --Reset the output.

 qtemp <= '0';

 qbartemp <= '1';

elsif( rising_edge(clk) ) then

if(J='0' and K='0') then       --No change in the output

 NULL;

elsif(J='0' and K='1') then    --Set the output.

 qtemp <= '0';

 qbartemp <= '1';

elsif(J='1' and K='0') then    --Reset the output.

 qtemp <= '1';

 qbartemp <= '0';

else                           --Toggle the output.

 qtemp <= not qtemp;

 qbartemp <= not qbartemp;

end if;

end if;

end process;

end Behavioral;

Simulated Results:-

Video Explanation of Code:-