VHDL Implementation of 4-State Finite State Machine (FSM)

A finite-state machine (FSM) or finite-state automaton (FSA, plural: automata), finite automaton, or simply a state machine, is a mathematical model of computation. It is an abstract machine that can be in exactly one of a finite number of states at any given time. The FSM can change from one state to another in response to some external inputs; the change from one state to another is called a transition. A FSM is defined by a list of its states, its initial state, and the conditions for each transition.

VHDL Code:-

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-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    20:15:34 05/30/2017 

-- Design Name: 

-- Module Name:    mealy - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mealy is

    Port ( reset : in  STD_LOGIC;

           input : in  STD_LOGIC;

           output : out  STD_LOGIC;

           clk : in  STD_LOGIC);

end mealy;

architecture Behavioral of mealy is

type state_type is (s0,s1,s2,s3);  --type of state machine.

signal current_s,next_s: state_type;

begin

process (clk,reset)

begin

 if (reset='1') then

  current_s <= s0;  --default state on reset.

elsif (rising_edge(clk)) then

  current_s <= next_s;   --state change.

end if;

end process;

process (current_s,input)

begin

  case current_s is

     when s0 =>        --when current state is "s0"

     if(input ='0') then

      output <= '0';

      next_s <= s1;

    else

      output <= '1';

      next_s <= s2;

     end if;   

     when s1 =>        --when current state is "s1"

    if(input ='0') then

      output <= '0';

      next_s <= s3;

    else

      output <= '0';

      next_s <= s1;

    end if;

    when s2 =>       --when current state is "s2"

    if(input ='0') then

      output <= '1';

      next_s <= s2;

    else

      output <= '0';

      next_s <= s3;

    end if;

  when s3 =>         --when current state is "s3"

    if(input ='0') then

      output <= '1';

      next_s <= s3;

    else

      output <= '1';

      next_s <= s0;

    end if;

  end case;

end process;

end Behavioral;

Simulated Results:-

Video Explanation of the Code:-