VHDL Implementation of CD4040BC 12-Stage Ripple Carry Binary Counter

The CD4060BC is a 14-stage ripple carry binary counter,and the CD4040BC is a 12-stage ripple carry binary counter. The counters are advanced one count on the negative transition of each clock pulse. The counters are reset to the zero state by a logical “1” at the reset input independent of clock.

VHDL Code:-

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-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    13:19:24 06/09/2017 

-- Design Name: 

-- Module Name:    CD4040BC - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity CD4040BC is

    Port ( clk : buffer  STD_LOGIC;

           rst : in  STD_LOGIC;

           o : out  STD_LOGIC_VECTOR (11 downto 0));

end CD4040BC;

architecture Behavioral of CD4040BC is

component not_gate

port( a : in  STD_LOGIC;

           b : out  STD_LOGIC);

 end component;

component and_gate

Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end component;

component jk_ff

Port ( j,k : in  STD_LOGIC;

           clk : in  STD_LOGIC;

reset : in STD_LOGIC;

            Q : out  STD_LOGIC;

           Qbar : out  STD_LOGIC);

end component;

signal clk1 : STD_LOGIC;

signal a1 : STD_LOGIC;  signal n0 : STD_LOGIC;

signal n1 : STD_LOGIC; signal n2 : STD_LOGIC;

signal n3 : STD_LOGIC; signal n4 : STD_LOGIC;

signal q1 : STD_LOGIC; signal qb1 : STD_LOGIC;

signal q2 : STD_LOGIC; signal qb2 : STD_LOGIC;

signal q3 : STD_LOGIC; signal qb3 : STD_LOGIC;

signal q4 : STD_LOGIC; signal qb4 : STD_LOGIC;

signal q5 : STD_LOGIC; signal qb5 : STD_LOGIC;

signal q6 : STD_LOGIC; signal qb6 : STD_LOGIC;

signal q7 : STD_LOGIC; signal qb7 : STD_LOGIC;

signal q8 : STD_LOGIC; signal qb8 : STD_LOGIC;

signal q9 : STD_LOGIC; signal qb9 : STD_LOGIC;

signal q10 : STD_LOGIC; signal qb10 : STD_LOGIC;

signal q11 : STD_LOGIC; signal qb11 : STD_LOGIC;

signal qb12 : STD_LOGIC;

begin

clk <= clk1;

not0 : not_gate port map( a => rst, b => n0);

and1 : and_gate port map(a => clk1, b =>n0, c => a1);

not4 : not_gate port map( a => n0, b=>n4);

not1 : not_gate port map( a => a1, b => n1);

not2 : not_gate port map( a => n1, b =>n2);

not3 : not_gate port map( a => n2, b =>n3);

jkff1 : jk_ff port map(j =>n3, k=>n2,reset =>n4,clk=>clk, Q=>q1,Qbar=>qb1);

jkff2 : jk_ff port map(j =>q1, k=>qb1,reset =>n4, clk=>clk, Q=>q2,Qbar=>qb2);

jkff3 : jk_ff port map(j =>q2, k=>qb2,reset =>n4 ,clk=>clk, Q=>q3,Qbar=>qb3);

jkff4 : jk_ff port map(j =>q3, k=>qb3,reset =>n4 ,clk=>clk, Q=>q4,Qbar=>qb4);

jkff5 : jk_ff port map(j =>q4, k=>qb4,reset =>n4, clk=>clk, Q=>q5,Qbar=>qb5);

jkff6 : jk_ff port map(j =>q5, k=>qb5,reset =>n4 ,clk=>clk, Q=>q6,Qbar=>qb6);

jkff7 : jk_ff port map(j =>q6, k=>qb6,reset =>n4,clk=>clk, Q=>q7,Qbar=>qb7);

jkff8 : jk_ff port map(j =>q7, k=>qb7,reset =>n4,clk=>clk, Q=>q8,Qbar=>qb8);

jkff9 : jk_ff port map(j =>q8, k=>qb8,reset =>n4 ,clk=>clk, Q=>q9,Qbar=>qb9);

jkff10 : jk_ff port map(j =>q9, k=>qb9,reset =>n4,clk=>clk, Q=>q10,Qbar=>qb10);

jkff11 : jk_ff port map(j =>q10, k=>qb10,reset =>n4, clk=>clk, Q=>q11,Qbar=>qb11);

jkff12 : jk_ff port map(j =>q11, k=>qb11,reset =>n4,clk=>clk, Qbar=>qb12);

not5 : not_gate port map(a=>qb1,b=>o(0));

not6 : not_gate port map(a=>qb2,b=>o(1));

not7 : not_gate port map(a=>qb3,b=>o(2));

not8 : not_gate port map(a=>qb4,b=>o(3));

not9 : not_gate port map(a=>qb5,b=>o(4));

not10 : not_gate port map(a=>qb6,b=>o(5));

not11 : not_gate port map(a=>qb7,b=>o(6));

not12 : not_gate port map(a=>qb8,b=>o(7));

not13 : not_gate port map(a=>qb9,b=>o(8));

not14 : not_gate port map(a=>qb10,b=>o(9));

not15 : not_gate port map(a=>qb11,b=>o(10));

not16 : not_gate port map(a=>qb12,b=>o(11));

end Behavioral;

Stimulated Results:-

Code Explanation in Video:-