VHDL Implementation of 3-STATE Quad 2-Data Selector/Multipliers DM74LS257B

This device is designed to multiplex signals from four-bit sources to four-output data lines in bus-organized systems. The 2-state outputs will not load the data lines when the output control pin is at a high-logic level.

VHDL Code:-

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-- Company: VHDL Language

-- Engineer: Manohar Mohanta

-- 

-- Create Date:    14:39:38 06/10/2017 

-- Design Name: 

-- Module Name:    LS256 - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity LS256 is

    Port ( c : in  STD_LOGIC;

           a : in  STD_LOGIC_VECTOR (3 downto 0);

 b : in  STD_LOGIC_VECTOR (3 downto 0);

           s : in  STD_LOGIC;

           y : out  STD_LOGIC_VECTOR (3 downto 0));

end LS256;

architecture Behavioral of LS256 is

component or_gate 

Port (  a : in  STD_LOGIC;

 b : in  STD_LOGIC;

 c : in  STD_LOGIC;

 d : out  STD_LOGIC);

end component;

component and_gate

Port (  a : in  STD_LOGIC;

 b : in  STD_LOGIC;

 c : out  STD_LOGIC);

end component;

component not_gate

Port (  a : in  STD_LOGIC;

 b : out  STD_LOGIC);

end component;

signal s1: STD_LOGIC; signal s2: STD_LOGIC;

signal s3: STD_LOGIC; signal s4: STD_LOGIC;

signal s5: STD_LOGIC; signal s6: STD_LOGIC;

signal s7: STD_LOGIC; signal s8: STD_LOGIC;

signal s9: STD_LOGIC; signal s10: STD_LOGIC;

signal s11: STD_LOGIC;

begin

not0 : not_gate port map( a => c, b => s11);

not1 : not_gate port map( a => s, b => s1);

not2 : not_gate port map( a => s1, b => s2);

and0 : and_gate port map( a =>a(0), b => s1, c => s3); 

and1 : and_gate port map( a =>b(0), b => s2, c => s4); 

and2 : and_gate port map( a =>a(1), b => s1, c => s5); 

and3 : and_gate port map( a =>b(1), b => s2, c => s6); 

and4 : and_gate port map( a =>a(2), b => s1, c => s7); 

and5 : and_gate port map( a =>b(2), b => s2, c => s8); 

and6 : and_gate port map( a =>a(3), b => s1, c => s9); 

and7 : and_gate port map( a =>b(3), b => s2, c => s10);

or0 : or_gate port map( a =>s3, b => s4, c => s11, d =>y(0));

or1 : or_gate port map( a =>s5, b => s6, c => s11, d =>y(1));

or2 : or_gate port map( a =>s7, b => s8, c => s11, d =>y(2));

or3 : or_gate port map( a =>s9, b => s10, c => s11, d =>y(3));

end Behavioral;

Simulated Results:-

Code Explanation:-