Basic Logical Or Gate Programming In VHDL Language

VHDL Program For "OR Gate"
----------------------------------------------------------------------------------
-- Company: vhdltutorials.blogspot.com
-- Engineer: G.Anitha
--
-- Create Date:    13:16:39 06/18/2014
-- Design Name:     G.Anitha
-- Module Name:    orgate - Behavioral
-- Project Name:    Basic Logical or gate
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity orgate is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end orgate;

architecture Behavioral of orgate is

begin
c <= a or b;

end Behavioral;

Simulated Result:-