Basic Logical AND Gate Program In VHDL Language

 VHDL Program for AND Gate

--------------------------------------------------------------
-- Company: VHDLtutorials.blogspot.com
-- Engineer: G.Anitha
--
-- Create Date:    13:16:39 06/18/2014
-- Design Name:     G.Anitha
-- Module Name:    and gate - Gate level
-- Project Name:    Basic Logical and gate
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity andgate is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end andgate;

architecture Behavioral of andgate is

begin
c <= a and b;

end Behavioral;

Simulated Result: