Introduction:-

In computing, a linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state.The most commonly used linear function of single bits is exclusive-or (XOR). Thus, an LFSR is most often a shift register whose input bit is driven by the XOR of some bits of the overall shift register value.The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits that appears random and has a very long cycle.

Abstract:-

Low power testing in VLSI has emerged as a standard idea in today!s electronics industry. The need for low power is root for a major pattern shift where power consumption has become a significant concern while comparing with performance and area. This work explores XOR network with Linear Feedback Shift Register (LFSR), which is having different tap connection. The proposed work is associated with general LFSR and modified LFSR with proper seed selection. This technique produces different input patterns and targeted to reduce transition switching of the bits. The experimental result is verified by XILINX Vertex 6 low power FPGA.

`timescale 1ns / 1ps
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// Company: VHDL Language
// Engineer: Manohar Mohanta
// 
// Create Date:    20:49:19 11/16/2017 
// Design Name:  Verilog Implemenation of DESIGN AND ANALYSIS OF SCAN POWER REDUCTION BASED ON LINEAR FEEDBACK SHIFT REGISTER RESEEDING
// Module Name:    MISR_LFSR 
// Project Name:  DESIGN AND ANALYSIS OF SCAN POWER REDUCTION BASED ON LINEAR FEEDBACK SHIFT REGISTER RESEEDING
// Target Devices: 
// Tool versions: 
// Description: 
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// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module MISR_LFSR(
    input [3:0] seed,
    input clk,
    input rst,
    output [8:0] signature
    );
  wire [8:0]w;
xor_network n (seed,w);
sig_reg MISR (w,clk,rst,signature);

endmodule