VHDL Implementation of 2-bit Vedic Multiplier

Vedic Multiplier 2-bit

The Vedic multiplier is designed by using the 2-bit gate level Vedic multiplier.The 2-bit gate level Vedic multiplier proposed in this project. By combining the four 2-bit Vedic multipliers, we have designed 4-bit Vedic multiplier. Normal 4-bit parallel adders are used to add the partial products of 4 2-bit Vedic multipliers.

You can Find the Code Where You can Learn How to implement it.

Code For Vedic Multiplier 2-bit

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-- Company: VHDL Language
-- Engineer: Manohar Mohanta
-- 
-- Create Date:    14:33:07 11/17/2017 
-- Design Name: 		Vedic Multiplier
-- Module Name:    vedic_2bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vedic_2bit is
    Port ( a : in  STD_LOGIC_VECTOR (1 downto 0);
           b : in  STD_LOGIC_VECTOR (1 downto 0);
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end vedic_2bit;

architecture Behavioral of vedic_2bit is
signal s : std_logic_vector(3 downto 0);
begin

q(0)<= a(0) and b(0);
s(0)<=a(1) and b(0);
s(1)<=a(0) and b(1);
q(1)<=s(0) xor s(1);
s(2)<=s(0) and s(1);
s(3)<=a(1) and b(1);
q(2)<=s(3) xor s(2);
q(3)<=s(3) and s(2);
end Behavioral;

Simulation Results:-

Vedic Multiplier Simulation Result

Demo For 2-bit Vedic Multiplier