The Viterbi algorithm is a dynamic programming algorithm for finding the most likely sequence of hidden states – called the Viterbi path – that results in a sequence of observed events, especially in the context of Markov information sources and hidden Markov models.
The algorithm has found universal application in decoding the convolutional codes used in both CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications, and 802.11 wireless LANs. It is now also commonly used in speech recognition, speech synthesis, diarization, keyword spotting, computational linguistics, and bioinformatics. For example, in speech-to-text (speech recognition), the acoustic signal is treated as the observed sequence of events, and a string of text is considered to be the "hidden cause" of the acoustic signal. The Viterbi algorithm finds the most likely string of text given the acoustic signal.
The algorithm has found universal application in decoding the convolutional codes used in both CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications, and 802.11 wireless LANs. It is now also commonly used in speech recognition, speech synthesis, diarization, keyword spotting, computational linguistics, and bioinformatics. For example, in speech-to-text (speech recognition), the acoustic signal is treated as the observed sequence of events, and a string of text is considered to be the "hidden cause" of the acoustic signal. The Viterbi algorithm finds the most likely string of text given the acoustic signal.
Verilog code for Viterbi Encoder
module encoder
(
clk,
rst,
enable_i,
d_in,
valid_o,
d_out
);
input clk;
input rst;
input enable_i;
input d_in;
output reg valid_o;
output [1:0] d_out;
reg [2:0] cstate;
reg [2:0] nstate;
reg [1:0] d_out_reg;
assign d_out = (enable_i==1'b1)?d_out_reg:2'b00;
always @(*) begin
valid_o = enable_i;
case (cstate)
3'b000:
begin
if(d_in==1'b0)
begin
nstate = 3'b000;
d_out_reg = 2'b00;
end
else
begin
nstate = 3'b100;
d_out_reg = 2'b11;
end
end
3'b001:
begin
if(d_in==1'b0)
begin
nstate = 3'b100;
d_out_reg = 2'b00;
end
else
begin
nstate = 3'b000;
d_out_reg = 2'b11;
end
end
3'b010:
begin
if(d_in==1'b0)
begin
nstate = 3'b101;
d_out_reg = 2'b10;
end
else
begin
nstate = 3'b001;
d_out_reg = 2'b01;
end
end
3'b011:
begin
if(d_in==1'b0)
begin
nstate = 3'b001;
d_out_reg = 2'b10;
end
else
begin
nstate = 3'b101;
d_out_reg = 2'b01;
end
end
3'b100:
begin
if(d_in==1'b0)
begin
nstate = 3'b010;
d_out_reg = 2'b10;
end
else
begin
nstate = 3'b110;
d_out_reg = 2'b01;
end
end
3'b101:
begin
if(d_in==1'b0)
begin
nstate = 3'b110;
d_out_reg = 2'b10;
end
else
begin
nstate = 3'b010;
d_out_reg = 2'b01;
end
end
3'b110:
begin
if(d_in==1'b0)
begin
nstate = 3'b111;
d_out_reg = 2'b00;
end
else
begin
nstate = 3'b011;
d_out_reg = 2'b11;
end
end
3'b111:
begin
if(d_in==1'b0)
begin
nstate = 3'b011;
d_out_reg = 2'b00;
end
else
begin
nstate = 3'b111;
d_out_reg = 2'b11;
end
end
endcase
end
always @ (posedge clk,negedge rst)
begin
// $display("data in=%d state=%b%b%b data out=%b%b",d_in,reg_1,reg_2,reg_3,d_out_reg[1],d_out_reg[0]);
if(rst==1'b0)
cstate <= 3'b000;
else if(enable_i==1'b0)
cstate <= 3'b000;
else
cstate <= nstate;
end
endmodule
Simulated Results
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