VHDL Basic Program On Multiplexers(Mux) Using Case Statement

VHDL Basic Tutorial On Multiplexers(Mux) Using Case Statement

           
        A multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2ⁿinputs has n select lines, which are used to select which input line to send to the output.

CODE For The Mux Program in VHDL Language Using Case

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-- Company: vhdltutorials.blogspot.com
-- Engineer: Manohar Mohanta
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-- Create Date:    18:27:17 03/20/2015
-- Design Name:
-- Module Name:    mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity logicgate is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
 d: in STD_LOGIC;
 s : in STD_LOGIC_VECTOR(1 downto 0);
 m : out STD_LOGIC);
end logicgate;

architecture Behavioral of logicgate is
begin
process(a,b,c,d,s) is
begin
case s is
when "00"=> m<=a;
when "01" =>m<=b;
when "10" =>m<=c;
when others=> m<=d;
end case;
end process;
end Behavioral;

Simulated Results:-