Description:-
If we put a not gate in front of any OR gate then it is known as nor gate. In this the program is written in gate level modelling.
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VHDL program for nor gate
------------------------------------------------------------------------------------ Company: VHDLtutorials.blogspot.in
-- Engineer: G.Anitha
--
-- Create Date: 13:16:39 06/18/2014
-- Design Name: G.Anitha
-- Module Name: norgate - Gate Level
-- Project Name: Basic Logical nor gate
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity norgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end norgate;
architecture Behavioral of norgate is
begin
c <= a nor b;
end Behavioral;
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