Verilog HDL Implementation of the Add-Compare-Select (ACS)

A path metric unit summarizes branch metrics to get metrics for  2^{K-1}} paths, where K is the constraint length of the code, one of which can eventually be chosen as optimal. Every clock it makes  2^{K-1}} decisions, throwing off wittingly nonoptimal paths. The results of these decisions are written to the memory of a traceback unit.The core elements of a PMU are ACS (Add-Compare-Select) units. The way in which they are connected between themselves is defined by a specific code's trellis diagram.Since branch metrics are always >0, there must be an additional circuit preventing metric counters from overflow (it isn't shown on the image). An alternate method that eliminates the need to monitor the path metric growth is to allow the path metrics to "roll over"; to use this method it is necessary to make sure the path metric accumulators contain enough bits to prevent the "best" and "worst" values from coming within 2(n-1) of each other. The compare circuit is essentially unchanged.

A sample implementation of an ACS unit

It is possible to monitor the noise level on the incoming bit stream by monitoring the rate of growth of the "best" path metric. A simpler way to do this is to monitor a single location or "state" and watch it pass "upward" through say four discrete levels within the range of the accumulator. As it passes upward through each of these thresholds, a counter is incremented that reflects the "noise" present on the incoming signal.

Verilog code for Add-Compare-Select (ACS)

module ACS

(

   path_0_valid,

   path_1_valid,

   path_0_bmc,

   path_1_bmc,

   path_0_pmc,

   path_1_pmc,

   selection,

   valid_o,

   path_cost

);

   input       path_0_valid;

   input [1:0] path_0_bmc;

   input [7:0] path_0_pmc;

   input       path_1_valid;

   input [1:0] path_1_bmc;

   input [7:0] path_1_pmc;

   output reg        selection;

   output reg        valid_o;

   output      [7:0] path_cost;  

   wire  [7:0] path_cost_0;

   wire  [7:0] path_cost_1;

   assign path_cost_0  =  path_0_bmc + path_0_pmc;

   assign path_cost_1  =  path_1_bmc + path_1_pmc;

   assign path_cost      =  (valid_o?(selection?path_cost_1:path_cost_0):7'd0);   

   always @ (*)

   begin

      valid_o = 1'b1;

      case({path_0_valid,path_1_valid})

         2'b00:

         begin

            selection = 1'b0;

            valid_o   = 1'b0; 

         end

         2'b01:   selection = 1'b1;

         2'b10:   selection = 1'b0;

         2'b11:   selection = (path_cost_0 > path_cost_1)?1'b1:1'b0;

       endcase

   end

   

endmodule

Simulated Results