Basic Logical AND Gate Program For 3 Inputs In VHDL Language

Description:
       This is a program for 3 input andgate where and operation is performed for the first two inputs and its output is declared as signal. Again the and operation is performed for the obtained signal and the third input.

VHDL Program for 3_input AND Gate

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-- Company: vhdltutorials.blogspot.in
-- Engineer: G.Anitha
--
-- Create Date:    13:16:39 06/18/2014
-- Design Name:     G.Anitha
-- Module Name:    andgate - gate level
-- Project Name:    Basic Logical and gate
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity andgate3_input is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
 d : out STD_LOGIC);
end andgate3_input;

architecture Behavioral of andgate3_input is
signal s: std_logic;
begin
s <= a and b;
d <= s and c;

end Behavioral;

Simulated Result: